1. Field of the Invention
The present invention relates to a Delay Locked Loop (DLL), and in particular, to an analog mixed digital DLL.
2. Background of the Related Art
As the technology of a semiconductor memory device is advanced, memory chips are designed to operate at a high speed. An internal clock signal CLKint used for the memory chips is obtained by delaying an external clock signal CLKext for a predetermined time. Since there is a certain limit for delaying the external clock signal, in order to decrease the time delay between an external clock signal CLKext and an internal clock signal CLKint, the Phase Locked Loop (PLL) or Delay Locked Loop (DLL) is generally used.
FIG. 1 is a block diagram illustrating a related art analog mixed digital DLL that includes an input buffer 10, a digital delay unit 20, and an analog delay unit 30. The input buffer 10 buffers the external clock signal CLKext and outputs the input clock signal CLKin. The digital delay unit 20 sequentially delays a input clock signal CLKin and outputs delay clock signals CLKD1-CLKD3. The digital delay unit 20 further selects single delay clock signal CLK2 locked to the input clock signal CLKin among the delay clock signals CLKD1-CLKD3. The analog delay unit 30 performs an analog locking operation with respect to the selected delay clock signal CLK2 selected by the digital delay unit 20.
The digital delay unit 20 includes variable delay units 21-23 for sequentially delaying the input clock signal CLKin, a multiplexer 24 for sequentially comparing the input clock signal CLKin and the delay clock signals CLKD1-CLKD3 from the variable delay units 21-23 and outputting one delay clock signal CLK2 locked to the input clock signal CLKin, and a replica delay unit 25 for delaying the locked clock signal CLK2 by a duration tAC of the delay of the replica (not shown) and outputting the delay locked clock signal CLK2xe2x80x2 to the analog delay unit 30. Here, the variable delay units 21-23 are referred to as a voltage controlled delay unit that varies the delay ratios in accordance with a control voltage CV from the analog delay unit 30. The number of the variable delay units 21-23 is also variable.
The analog delay unit 30 includes a phase detector 31 for comparing the phase of the input clock signal CLKin and that of a delay clock signal CLK2xe2x80x2 from the digital delay unit 20 and outputting the pulse signals UP and DN, a charge pump 32 and a voltage controller 33. The charge pump 30 performs a pumping operation in accordance with the pulse signals UP and DN from the phase detector 31, and the voltage controller 33 outputs a control voltage CV for controlling the delay ratios of the variable delay units 21-23 in accordance with an output from the charge pump 32. The phase detector 31 is edge-triggered and can be implemented by an Exclusive OR-gate (XOR), a JK flip-flop and Phase Frequency Detector (PFD).
The operation of the related art analog mixed digital DLL will now be described. The input buffer 10 generates an input clock signal CLKin by buffering an external clock signal CLKext, and the generated input clock signal CLKin is inputted into the digital delay unit 20 and the analog delay unit 30, respectively. The variable delay units 21-23 of the digital delay unit 20 sequentially delay the input clock signal CLKin and output a plurality of delay clock signals CLKD1-CLKD3. The multiplexer 24 sequentially compares the delay clock signals CLKD1-CLKD3 and the input clock signal CLKin and searches for a locking point. The locking point is determined as a point in which the phase of the delay clock signal CLK2 is slower than that of the input clock signal CLKin based on the duration tAC of the delay of the replica.
For example, assuming that the delay clock signal CLKD2 is locked to the input clock signal CLKin, the locked delay clock signal CLK2 is delayed by the duration tAC of the delay of the replica by the replica delay unit 25, and the phase detector 31 of the analog delay unit 30 compares the phase of the input clock signal CLKin and that of the delay clock signal CLKD2xe2x80x2 from the replica delay unit 25. As a result of the comparison, if the phase of the delay clock signal CLKD2xe2x80x2 leads the input clock signal CLKin, the phase detector 31 generates the pulse signal DN having a prescribed width wider than the width of the pulse signal UP. If the phase of the delay clock signal CLKD2xe2x80x2 lags the input clock signal CLKin, the phase detector 31 generates the pulse signal DN having a predetermined width smaller than the width of the pulse signal UP.
If the width of the pulse signal DN is greater than that of the pulse signal UP, the driving capacity of the charge pump 32 is enhanced by the pulse signal DN so that the level of the control voltage from the voltage controller 33 is increased, and the duration of the delay of the variable delay units 21-23 is increased. If the width of the pulse signal UP is greater than that of the pulse signal DN, the driving capacity of the charge pump 32 is deteriorated by the pulse signal DN, and the level of the control voltage CV from the voltage controller 33 is decreased. In this case, the duration of the delay of the variable delay units 21-23 is decreased.
As the above-described processed are repeatedly performed, when the phases of the input clock signal CLKin and the delay clock signal CLKD2xe2x80x2 become identical, the widths of the pulse signals DN and LP from the phase detector 31 also become identical, so that the output from the charge pump 32 becomes a stable state. This state becomes the final locking state of the analog delay unit 30, and the locking clock signal CLK2 from the multiplexer 24 becomes the final internal clock signal CLKin.
The related art analog mixed digital DLL selects one delay clock signal of the delay clock signals CLKD1-CLKD3 locked to the input clock signal CLKin through the digital delay unit 20, and the analog delay unit 30 finally performs an detailed analog locking operation with respect to the selected delay clock signal CLKD1-CLKD3.
As described above, the related art analog mixed digital DLL has various disadvantages. In the related art analog mixed digital DLL, the multiplexer receives the delay clock signals from the variable delay units and compares the received delay clock signals and the input clock signal based on a 1:1 comparison. In this case, it takes long time to generate the final internal clock signal, and a data access time of the memory apparatus that uses the internal clock signals is increased.
In addition, to operate the related art analog mixed digital DLL in a band frequency range, a number of the variable delay units should be increased because the locking occurs in a front variable delay unit of the analog mixed digital DLL in the case of the low frequency, and the locking occurs in a rear variable delay unit of the analog mixed digital DLL in the case of the high frequency. Therefore, the number of the variable delay units should be increased when operating the analog mixed digital DLL in the wide band frequency range of the external clock signal. However, the jitter characteristic is degraded when the related art analog mixed digital DLL is operated in the high frequency region because of the variation of the operation voltage, the external noise and the temperature increase, so that multi-locking (a plurality of locking points) occurs. The multiple locking clock signals, which are generated by the multi-locking, theoretically have the same timing but have a prescribed timing difference. The clock timing of the final internal clock signals, which are outputted through the output buffer (not shown), may be changed based on the prescribed timing difference. In addition, the related analog mixed digital DLL increases the current consumption since the variable delay units after the locked variable delay unit are unnecessarily operated.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the present invention is to provide an analog mixed digital DLL that substantially overcomes one or more problems caused by disadvantages of the related art.
Another object of the present invention is to provide an analog mixed digital DLL that implements a wide band frequency operation and reduces jitters.
Another object of the present invention is to provide an analog mixed digital DLL, which has a noise immunity.
Another object of the present invention is to provide an analog mixed digital DLL that prevents a multi-locking in the wide band frequency operation.
Another object of the present invention is to provide an analog mixed digital DLL that generates an internal clock signal from an external clock signal within a short time.
Another object of the present inventions is to provide an analog used digital DLL that decreases current consumption.
To achieve at least the above objects in a whole or in parts, there is provided an analog mixed digital DLL according to in the present invention that includes an input buffer for buffering an external clock signal and outputting a first clock signal, a digital mode controller for comparing the phases of delay clock signals outputted from a plurality of delay blocks and a first clock signal, detecting an initial locking point, selecting one delay clock signal at the detected locking point and controlling the operation of the delay clocks, an analog mode controller for comparing the phase of the delay clock signal selected by the digital mode controller and the phase of the first clock signal, and a control voltage conversion switch for providing the externally inputted first control voltage or the second control voltage to the delay blocks in accordance with the digital and analog operation modes.
To further achieve the above objects, there is provided an analog mixed digital DLL according to the present invention that includes an input buffer for buffering an external clock signal and outputting a first clock signal, an analog mode controller for comparing the phases of a DLL-locked delay clock signal and a first clock signal and outputting a first voltage, a replica moving switch for moving the position of a replica, a control voltage conversion switch for switching first and second control voltages in accordance with the digital and analog operation modes, a delay block array formed of a plurality of delay blocks for varying the delay duration by the first and second control voltages for sequentially delaying the first clock signal, a multiplexer controller for comparing the phases of the delay clock signals from the delay block array and the first clock signal, outputting a locking signal, and outputting a control signal for controlling the path of the delay clock signals, a selection signal generator for receiving the control signal and outputting a selection signal, and a multiplexer for outputting one delay clock signal selected by the selection signal to the analog mode controller and outputting an enable signal for receiving a control signal from the multiplexer controller and controlling the delay blocks.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.